LVDS Receiver Test Board

This is a small board with a DS90CR286A LVDS deserializer (channel-link receiver) and appropriate connectors to mate with the RJ-45 signal output from a LTB. The receiver outputs are available on a 30-pin header connector.

Data format updated 2011-07-27 by E. Hazen

Layout

For bit functions and link protocol information, see Link Tx/Rx Page

Output Header Pinout

Note: The column "LRB Protocol Bit" in the table below corresponds to the original LRB/LTB protocol used in the D0-STT trigger. In the CMS HTR/DCC system the meaning of these bits is changed somewhat. In particular, bit 5 is no longer used due to crosstalk problems on the HTR PCB layout. The S0 protocol bit is manufactured by the DCC2 LRB firmware.

Pin No Data Bit LRB Protocol Bit (Old) HTR/DCC Protocol (New)
1 GND  
2 GND  
3 DATA-0 H0 H0
4 DATA-1 H1 H1
5 DATA-2 D0 D0
6 DATA-3 H2 H2
7 DATA-4 D1 D1
8 DATA-5 D2 -unused-
9 DATA-6 D3 D3
10 DATA-7 H3 H3
11 DATA-8 D4 D4
12 DATA-9 D5 D5
13 DATA-10 D6 D6
14 DATA-11 D7 D7
15 DATA-12 D8 D8
16 DATA-13 D9 S1
17 DATA-14 D10 D10
18 DATA-15 H4 H4
19 DATA-16 D11 D11
20 DATA-17 D12 D12
21 DATA-18 D13 D13
22 DATA-19 D14 D14
23 DATA-20 D15 D15
24 DATA-21 S0 D2
25 DATA-22 S1 D9
26 DATA-23 P P
27 GND    
28 GND    
29 CLOCK    
30 GND