Layout Notes

General

• Immersion gold surface finish (notes)
• Use .006/.006 rules.
• Everywhere there is a table titled "LEGEND" on the schematic with a list of pin numbers, the text should go on the silkscreen near the corresponding connector or testpoint.

• (Page 8 etc) HM3x5_LVDS map to 3 rows of pins on hard metric connector (see mechanical dwg). Row C pins should be grounded.
• Double-check hole size on press-fit connectors
• Please send BGA footprint and breakout routing plans for review
• Testpoints should be 10x2 0.1 in header (SMT okay)

• No auto-routing, please!
• LVDS Receivers
  • Page 8-11 R48 etc should be close to U7 etc (4 sheets) PAR_CLK nets (4) should be kept short.
  • Page 12. TP2 should be close to U7 so that stubs are short.
• LVDS pairs (J5-J16 traces)
  • All pairs as short as practical
  • route on top/bottom only
  • 2 traces in pair match to 5mm
  • 100 ohm r's close to IC's
  • pairs match to 1cm within group of 5
  • PAR[27:0] + PAR_CLK to FPGA match to 5cm
• Xilinx FPGA
  • (Page 5) - Output of Y1 (G_CLK) should be short (5cm max)
  • (Page 6) - R43 should be near U4. R42 should be near J4
  • The TCK and CCLK nets should be as short as possible.
• Backplane Bus (Page 21)
  • IC's (U19-U25 and U31) should be near JP1. U23 and U31 LVDS pairs (those with P/N types) should follow rules:
    • All pairs as short as practical
    • route on top/bottom only
    • 2 traces in pair match to 5mm
  • MCLK, NRZC nets from FPGA should be kept short and same length within few cm. R53 and R54 should be near FPGA.
• SLDB, SCL daughterboards
  • match all within one DB to 5cm
  • (Page 22) ICs (U26-U29) should be near connectors. R45 should be near U28.
  • TP4 should be near connectors to minimize stub lengths.
  • (Page 23, 24). R47 should be near J17, and R48 near J19.
  • TP5 and TP6 should be near J17 and J19 to minimize stub lengths.
• Power supplies (Page 2)
  • 3.3V, GND - solid planes
  • no thermal relief on vias
  • 1.5V - copper pour covering BGA power pins and bypass caps
  • All components onnected to U1 (LT1765) must be very close, and connected with heavy traces / pours.
    Sample, see schematic and corresponding photo.
    C7 should be near J1, and C8 should be near the BGA.