2005-01-25

	* All files renamed to dsat_revxx for consistency
	* current version (rev07) is in dsat2_rev07a.zip
	* source files added in dsat2_rev07a_vhdl.zip

2004-08-26

	* dsat_v2_rev04.zip
	  All 8 LVDS Tx, 4 LVDS Rx now working
	  Both bit and mcs (prom) files included

2004-08-23

        * <dsat2_top_rev03b.bit> should fix slot latch problem.
	     ./dfea_rw -w 0xf800 0
          should set the slot latch to 0

	* Fixed (hopefully) DFEA reads.  Use <dsat2_top_rev03a.bit>
	  for now DTACK is ignored; read is done on first cycle
	  following AS cycle

2004-08-20

	* DFEA backplane timing is messed up.  Writes work, reads don't
	dsat2_top_rev03.bit is a failed attempt to fix this!

2004-08-18

	* Rev 02 - most things working
	*   see spec in Docs/ subdirectory for details

	* Untitled_1.mcs - program in first Prom in JTAG chain
	* Untitled_0.mcs - program in 2nd Prom in JTAG chain


2004-08-12    <hazen@joule.bu.edu>

	* First release:  ver 0x01
	*   address 0 always reads 0xd5a10001
	*   address 1 is 32-bit read/write test register

	*   address 0x10 is backplane address latch (R/W)
	*   address 0x11 is backplane data (write triggers BP write cycle)
	*   address 0x12 is backplane CSR:
	*      write '1' to bit 1 to trigger backplane read to data reg